The semiconductor industry has a need to access many electronic devices on a semiconductor wafer. As the semiconductor industry grows and devices become more complex, many electrical devices, most commonly semiconductor devices, must be electrically tested, for example, for leakage currents and extremely low operating currents. These currents are often below 100 fA. In addition, the currents and device characteristics are often required to be evaluated over a wide temperature range to understand how temperature affects a device, thereby having controllable device characteristics. To effectively measure at currents below 100 fA, a measurement signal must be isolated from external electrical interference, leakage currents through the dielectric material, parasitic capacitance, triboelectric noise, piezoelectric noise, and dielectric absorption, etc.
Additionally, due to the wide variety of die pitches (referring to the spacing between adjacent devices on a die/wafer or the corresponding spacing between adjacent probe tiles on a base plate), users need the flexibility of reusing probe tiles in a variety of base plates. These base plates match different die pitches. Die pitch relates to the size of a die. The size of a die pitch may vary, for example, from 10 mm2 to 30 mm2, etc. Further, the shape of a die pitch may vary as well, for example, a rectangular shape, a square shape, etc.
At present, semiconductor test equipment is designed such that a user has to use different probe tiles (or sometimes referring to as “probe cards”) if the size or shape of die pitches on a die/wafer is different.
Thus, it is desirable to have a probe apparatus that allows the flexibility of reusing probe tiles. Further, it is desired that external electrical interference, leakage currents through the dielectric material, parasitic capacitance, triboelectric noise, piezoelectric noise, and dielectric absorption are significantly reduced or eliminated.